DDR3 Memory Timings Explained

Author xmad on 29 August, 2012 | Print | Bookmark


DDR3: Double Data Rate synchronous dynamic random access memory version 3
Double Data Rate means that this memory transfers data on both the rising and falling edges of the clock signal. This is why 1600mhz DDR3 memory appears as 800MHz in cpuid. This is the current type of memory used in modern systems. It is not backward compatible with any other type or memory.

Timings: When we are talking about timings, we are talking about the speed at which the memory controller access's reads and writes from one 64bit block to another. When you see ram timings, they are generally represented like this: 9-9-9-24 or CL- tRCD-tRP-Tras (See below) there are more advanced ram timings, but these are the most important and we will cover the others later.

CAS timing or CL: CAS stands for Column Address Strobe It controls the number of CPU cycles between sending a reading command and the time to act on it. Setting this to a lower number will increase performance.

RAS to CAS delay or tRCD: Is the amount of time in cycles for issuing an active command and the read/write commands.

Row Precharge Time or TRP: The minimum # of clock cycles between  active commands and read/write cycles of the next bank on the memory module.

Min RAS Active Time or tRAS: This is the amount of time between a row being activated by precharge and deactivated. A row cannot be deactivated until the tras limit is reached. When overclocking your timings, you must keep the tRAS = CL + tRCD+tRP (+/-1)

Command Rate: This controls the number of cycles that memory commands can be executed. 1T is the highest performance, the higher the command rate, the More stable the system.

JEDEC memory Standards:
"The JEDEC memory standards are the specifications for semiconductor memory circuits and similar storage devices promulgated by the JEDEC Solid State Technology Association, a semiconductor trade and engineering standardization organization."
"JEDEC Standard 100B.01 specifies common terms, units, and other definitions in use in the semiconductor industry. JESC21-C specifies semiconductor memories from the 256 bit static RAM to the latest DDR3 SDRAM modules." For our purposes, basically this group sets what is standard in regards to how memory should perform in relation to speed  & Timings.

The table below shows how memory is supposed to be timed in order to be "standard". Any lower timing at a given speed is considered out of spec or overclocking. Most of the time at a given speed, so long as the CPU and board are designed for the data rate/ bandwidth, ANY memory should be able to operate at that standard.

The Intel® Extreme Memory Profile
Intel® Extreme Memory Profile (Intel® XMP) allows you to overclock compatible DDR3 memory to perform beyond standard specifications. This is an automatic overclocking profile tested by the manufacturer of the memory. This profile is stored on the memory itself and is able to be accessed and applied by the bios of your mother board.
Sorry AMD guys, you have to do this manually, although by looking at the spd profile, you can manually match the timings / speed.

SPD: Serial presence detect is a standard way that information on how the memory is designed to run that is stored the memory itself. This is usually comprised of several JEDEC standard profiles and an XMP profile. The bios is able to pull this information from the memory in order to properly use the memory. This of course can be overridden which is the whole point of overclocking, but this is always the starting point.

Below is a screen shot of the spd as displayed by CPUID.
As you can see, the ram shown was sold as DDR3 2133, but it can only run at 1333 and still be within JEDEC spec! Also, you can see that it's max rated bandwidth is 1333! So really it is overclocked DDR3 1333 sold as DDR3-2133! Currently, the highest rated memory available is 1866 but is almost impossible to find or afford if you do, almost everything you see available for purchase is 1333 or at most 1600!

Dram Voltage: The amount of Voltage Applied to the Memory; The JEDEC standard for DDR is 1.5v +- .075 with the exception of DDR3L which is 1.35v
"According to JEDEC, 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level."

VTT/ VCCIO/ I/O: This is the voltage applied to the memory controller and is often overlooked in overclocking. Remember that as you raise your CPU overclock you are also increasing the memory bandwidth. So many people over compensate with CPU Voltage when less of that and more I/O voltage would have done the trick.

Advanced Memory Timings

In this section I will be detailing the advanced ram timings. Unless you are really dedicated to overclocking / tinkering, it is safe to say you can stop here and leave all of these on auto. Other wise, here we go....

Memory Rank: A memory rank is a set of DRAMs connected to the same chip select, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).

Memory Refresh: Memory refresh is the process of periodically reading information from an area of computer memory, and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information.

Memory Bank: A memory bank is a logical unit of storage in electronics, which is hardware dependent. In computer the memory bank may be determined by the memory access controller and the CPU along with physical organization of the hardware memory slots.

Row Cycle Time or tRC:This sets the number of cpu cycles a memory row (Remeber that memory is devided into "cells" much like an excel spredsheet) takes to complete a full cycle. A full cycle is from row activation to precharging of the active row. This setting has major affect on memory speed w/ a lower timing being faster. tRC= tras + tRP

Refresh to Activate Delay / Refresh Cycle Time or tRFC: Sets the number of clock cycles from the refresh command until the first activate command to the same rank.

Refresh Mode Select / Refresh Period or tREF: Sets the number of clock cycles refreshes will be executed. HIGHER VALUE FOR HIGHER PERFORMANCE

Performance Level / Read Delay or tRD: Sets the number of memory clocks from DRAM chip select# assert to host data ready# assertion on the FSB.
Translation:  Whenever the FSB and MEMORY speed are increased, the tRD and Northbridge voltage(I/O see above) will have to be increased in order to handle the addtional bandwidth.  This setting has MAJOR effects on both performance and stability. This should be set to the lowest stable setting at any Speed.

Write to Precharge Delay / Write Recovery Time or tWR: This sets the number of clock cycles between the completion of a valid write operation and before an active bank can be precharged. Write to precharge formula is tCL -1 +(Burst Legnth / 2)+tWTR

Activate to Activate delay or tRRD: Number of clock cycles between the activation of two rows in different banks of the same rank. (not much of a performance boost)

Read to Precharge delay or tRTP: The number of clock cycles between a read command to a row pre-charge command of the same rank.

Read to Write delay or tRTW: The number of clock cycles between a read command and a write command of the same rank.

Four Activate Window or tFAW: The number of cycles in which four activates are allowed within the same rank.

Precharge to Precharge delay or tPTP: The number of cycles between precharge commands of different banks of the same rank.

Write / Read command spacing or tWR-RD: The number of clocks between a write command and a read command of a different rank.

Read / Write Command Spacing or tRD-WR:The number of clocks between a write command and a write command of different ranks in the same channel.

Force Auto Precharge: Forces auto precharing for every reand and write command. Enabled for power savings

Maximum Asynchronous Latency: Sets the maximum latency of a round trip from the cpu to dram and back. This is specifed in NB clock and includes asynchronous and synchronous latencies.

Read/Write Queue Bypass: The number of times that the oldest operation in the Dram controller read/write queue may be bypassed.

Queue Bypass Max: The max number of times that the oldest memory -access request in the Dram controller queue may be bypassed.

Dram Idle Timer: The number of clocks the Dram Controller will remain in the idle state before it begins precharging all pages.

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