enabling CEP results in better performance at particular settings

charonme

charonme

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I'm trying to draw a performance/power limits curve for my 14700K, setting progressively lower power limits and doing a short 4minute CB R23 run to get the score at each power limit with LLC4, AC/DC 18/32, CEP on, -0.1V offset. I thought I already picked a high enough AC_LL not to trigger CEP clock stretching, but around PL1=PL2=190W I noticed a slight dip in the scores. So I checked if it was caused by CEP and turned CEP off and sure enough even at AC=18 LLC4 CEP was still kicking in at PL=190W (but not at different power limits around that). So I tried some other higher AC values and adjusted the offset accordingly.

Now I'm trying AC/DC 52/32 and -0.145V offset. So far from PL=270W down to PL=160W I got a smooth curve of decreasing CB R23 scores, but at 150W and 140W it suddenly dipped sharply from the curve. So again I checked if it's CEP and turned CEP off and tried again, but this time I got 1151 FEWER points with CEP off. Also the average P-core frequencies were 164MHz smaller, average vcore around 13mV higher and temperatures also slightly higher with CEP off. I switched CEP on and off back and forth a couple of times and measured the scores to ensure it's not some fluke, but it's quite consistent. At these settings I really get better performance with CEP turned on. I also tried some other higher power limits with and without CEP and those are also better with CEP. What's going on? I thought CEP could only cause worse performance. (Also there is still that lesser mystery of the dipping score below 160W)
 
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That’s very interesting “Intel.“ We do know from BuildZoid’s tests that CEP has two dominant characteristics: 1) it alters core frequencies when it thinks it needs to, and 2) it only reacts to voltage drops of a certain steepness/variety. So, if we thought about it long enough, I’m sure we could figure out what’s going on. It might imply that CEP is quicker to react (both ways) than the traditional PL1/PL2 throttling. In other words, it has better recovery time.

I would have to believe that we are dealing with some real edge conditions here. But either way, it’s very interesting behavior. I’m going to continue thinking about this one. But maybe Vassil_V will have an immediate “of course“ kind of explanation. I’m looking forward to that one!
 
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Here's a question for you to think about, Charonme: What do you think happens when your CPU hits the PL2 power limit? And then think about how CEP might see that.
 
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I checked with low enough max frequencies not to trigger any throttling limits and it appears with CEP off the power usage is slightly higher than with CEP on (both the max power and average power are higher without CEP by around 3-4% in my tests so far), but the CB R23 score remains the same
 
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hwinfo package power measurement during a couple of CB R23 loops with PL1=210W and PL2=230W: blue=CEP on (score was 33913), red=CEP off (score 33548)
green = average Pcore frequencies CEP on, yellow = average Pcore frequencies CEP off
cbr23_power_cepon_blue_cepoff_red.png
cbr23_avg_pcore_freq_cepon_green_cepoff_yellow.png
 
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Man, it‘s such nuanced stuff, it's hard to see what CEP is doing. The score difference is also statistically as small (1.08%) as the oscilloscope differences. Do you think CEP is just reacting quicker and recovering quicker when near the limit? I'd love to know what that CEP "black box" was intended to do.
 
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clamp ammeter EPS cable measurement falsifies the hypothesis that turning CEP off overestimates the internal power measurement and makes the power limits throttle sooner without CEP:
limited max P-core ratios to 52, E-core ratios to 42 to prevent power limit or thermal throttling, 4 minute CB R23:
CEP onCEP off% higher
max power (hwinfo reading)218.515 W230.466 W5.19%
avg power (hwinfo reading)206.5 W219.1 W5.75%
CB R23 score34629346970.2%
max EPS cable measurement23.4 A24.7 A5.26%
max EPS power (current * 12V)280.8 W296.4 W5.26%

so it appears disabling CEP makes the same frequencies draw 5% more power at the same performance in CB R23 (at least with my 2023 old bios and microcode)

I also tried with AVX turned off, it was even worse (5.93%)
with AVX off, C-states off, EIST off, speed shift off it's 6.28%
 
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charonme said:
clamp ammeter EPS cable measurement falsifies the hypothesis that turning CEP off overestimates the internal power measurement and makes the power limits throttle sooner without CEP:
limited max P-core ratios to 52, E-core ratios to 42 to prevent power limit or thermal throttling, 4 minute CB R23:
CEP onCEP off% higher
max power (hwinfo reading)218.515 W230.466 W5.19%
avg power (hwinfo reading)206.5 W219.1 W5.75%
CB R23 score34629346970.2%
max EPS cable measurement23.4 A24.7 A5.26%
max EPS power (current * 12V)280.8 W296.4 W5.26%

so it appears disabling CEP makes the same frequencies draw 5% more power at the same performance in CB R23 (at least with my 2023 old bios and microcode)

I also tried with AVX turned off, it was even worse (5.93%)
with AVX off, C-states off, EIST off, speed shift off it's 6.28%
Click to expand...
I‘d still love someone to tell me why CEP reduces power consumption even when Performance is seemingly unaffected. My poor brain can’t figure that one out.

Are you planing on doing the same experiments with the latest BIOS? I wouldn’t be surprised if Intel tweaked everything, including CEP behavior. It’s very interesting and methodical work you are doing, charonme. You got me hooked!
 
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I'd like to know too! This time I tried AC/DC 28/32 and -0.135v offset with max P/E core multipliers 51/41 and all stats were around 0.7% higher with CEP off (including the CB score) - I guess maybe that was already triggering CEP clock stretching?

I plan to update the bios gradually to newer and newer versions, although I'll probably skip the beta versions. I first need to get some hold on what's it doing now and record some stats at different settings to see how it will be affected by a new bios or microcode

Right now I'm trying LLC5 because it seems to me LLC4 is giving me more voltage with higher load at the same frequencies (probably due to thermal voltage adjustments) and I'd like to flatten it out a bit with the hope I can get lower stable voltages. So I set LLC5, zero offset and found AC/DC=44/44 is the one that has vcore=VID in allcore heavy load. Then I added a -0.14V offset and now with PL=210 I'm getting CB R23 (4min) 35314 with CEP and 34701 without CEP
 
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Myrdhinn said:
Nice scores. Wish I could try this but alas, z690 has no LLC setting.
Click to expand...
No way? It should be on the “Advanced CPU configuration” screen It’s on the DigiPower (or Digi-something) sub menu from main Overclocking screen, and it’s called “Loadline Calibration Control” - it has user settings 1 - 8 and an Auto setting. We call it LLC for short.
 
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FlyingScot said:
No way? It should be on the “Advanced CPU configuration” screen It’s on the DigiPower (or Digi-something) sub menu from main Overclocking screen, and it’s called “Loadline Calibration Control” - it has user settings 1 - 8 and an Auto setting. We call it LLC for short.
Click to expand...
Hmmm.... I'll have to recheck, maybe I was looking in the wrong place. heh, occupational hazzard. ;p
 
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Another test with loading 1 P-core with various consecutive loads (CB R23, P95, OCCT, y-cruncher, linpack) limited to max 5.1GHz (disabled C-states, Speed Shift, EIST, TVB).
It appears without CEP the core often asks for approx 4mV more than with CEP (especially in load).

[edit] beware, this might have been distorted by an additional E-core, see next attempt for a correction
1Pcore_cep_test.png
 
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Okay….I’m not sure if this is relevant but BuildZoid has notice that Raptor Lake CPUs are less sensitive to Vdroop crashes than older generations. Perhaps the extra 4mV is part of that equation, so to speak. Then CEP strips it away because it can clock-stretch when necessary to “catch” the Vdroop crash before it happens. The implications of this approach is that you are getting more voltage all the time (with CEP off) even if you don’t need it. With CEP enabled, and a properly tuned CP_LL/LLC and manual voltage, you get neither the extra voltage nor the clock-stretching. So more potential for higher auto-boost performance (possibly) and less heat. If that last statement is true, with a fixed Core Ratio, you would expect exactly the same performance. Is that what you saw? I guess your frequency graph would give me that answer, if I could read it with these old eyes.

Btw, when you say you disabled TVB, what do you mean? What BIOS settings did you change? TVB is an odd animal in the way it works. My understanding is/was that you cannot really disable it, you can only adjust its behavior as it relates to temperature threshold. Can you elaborate in case I missed something. Thanks! EDIT: I guess a manual Core Ratio would ”disable it”.
 
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I just disabled these settings in my bios: TVB Ratio Clipping, TVB Ratio Clipping Enhanced, TVB Voltage Optimizations in an attempt at minimizing the influence of temperature. I also increased the fan speeds considerably just in case.
I haven't measured the performance and I didn't fix the ratio, I just limited it to max x51. The graphed value is the "effective frequency" in hwinfo. Unfortunately I haven't time-synchronized the various loads, so it looks a bit chaotic. Maybe I'll do it again and sync the load times. From my previous tests with limited ratios I'd expect the performance to be the same.
 
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the previous test could have been distorted by an E-core and maybe also hyperthreading, so I disabled HT and all E-cores and fixed 2 P-cores to x52
2pcores_sync_load_cep_test.png
 
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