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- Nov 2, 2006
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INEGRATED MEMORY CONTROLLERS - CHANGING THE DEPENDENCIES OF COMPUTING
An IMC is the memory controller hub of a chipset integrated into a CPU. MCHs control the operation of memory.
AMD was the first (for performance reasons) to have an on-die memory controller back in 2003, with the Athlon 64 [Sledgehammer] generation of CPUs. Since then, the IMC has been carried from generation to generation, and eventually adopted by Intel in the Core i7 [Nehalem] generation of CPUs.
Since the IMC's integration, many believe there isn't a northbridge on mainboards. No MCH doesn't mean there is no northbridge on the board. The northbridge is the chip on the north of the board, the southbridge is the chip on the south. Simple.
Before IMCs, a computer diagram looked like this:
Can you see how the memory is interconnected with the NB? This causes data transfer to take longer with higher latency [delay]. But the board is responsible for the well-being of this MCH.
IMCs IN MODERN SYSTEMS:
INTEL CORE I7
In the Nehalem generation of CPUs, Intel moved the MCH [Memory Controller Hub] into the CPU. It's tri-channel, and supports up to DDR-1333, respectively. Going over these speeds is overclocking; which is never guaranteed.
Note how the NB is still present, but now only serves PCI-E functions.
INTEL CORE I5
Intel has given more of the NB's [IOH's] functions to the CPU. In this case: PCI-E. The supported PCI-E configurations are x16/x0 and x8/x8.
As you can also see, the legacy southbridge (ICHx) has now disappeared too.
AMD PHENOM II, ATHLON 64 (AM2+/AM3)
Phenom II's dual channel DDR2/DDR3 controller supports DDR-1066 on DDR2, and DDR-1333 on DDR3, respectively. Going over these speeds is overclocking; which is never guaranteed.
Can you see how the memory is interconnected with the CPU, and not the NB as in previous generations? This is the big change which allows those massive bandwidth figures, and ultra-low latency times.
<hr>
GETTING DECENT DDR2/DDR3 SPEEDS
On DDR2/DDR3, when you go beyond about 1000 MHz with DDR2 and 1333 MHz with DDR3, there's a special thing you need to do. Most people only set CAS, tRCD, tRP and tRAS to the specified timings. While this is necessary, it is also not enough. If you're using a chipset that supports EPP/XMP, I suggest you use these profiles because the advanced memory timings will be applied. When overclocking, the advanced timings are not changed, and usually cause unstable overclocks.
The timing you need to start working with is tRFC. tRFC can go as high as 72T when you go to 1800 MHz. Download Everest, view your SPD profile, and make note of the tRFC setting in your sticks EPP/XMP profiles if you wish to overclock manually. If no EPP/XMP profiles are present, unfortunately, you will have to guess.
<hr>
Thanks for reading.
An IMC is the memory controller hub of a chipset integrated into a CPU. MCHs control the operation of memory.
AMD was the first (for performance reasons) to have an on-die memory controller back in 2003, with the Athlon 64 [Sledgehammer] generation of CPUs. Since then, the IMC has been carried from generation to generation, and eventually adopted by Intel in the Core i7 [Nehalem] generation of CPUs.
Since the IMC's integration, many believe there isn't a northbridge on mainboards. No MCH doesn't mean there is no northbridge on the board. The northbridge is the chip on the north of the board, the southbridge is the chip on the south. Simple.
Before IMCs, a computer diagram looked like this:
Can you see how the memory is interconnected with the NB? This causes data transfer to take longer with higher latency [delay]. But the board is responsible for the well-being of this MCH.
IMCs IN MODERN SYSTEMS:
INTEL CORE I7
In the Nehalem generation of CPUs, Intel moved the MCH [Memory Controller Hub] into the CPU. It's tri-channel, and supports up to DDR-1333, respectively. Going over these speeds is overclocking; which is never guaranteed.
Note how the NB is still present, but now only serves PCI-E functions.
INTEL CORE I5
Intel has given more of the NB's [IOH's] functions to the CPU. In this case: PCI-E. The supported PCI-E configurations are x16/x0 and x8/x8.
As you can also see, the legacy southbridge (ICHx) has now disappeared too.
AMD PHENOM II, ATHLON 64 (AM2+/AM3)
Phenom II's dual channel DDR2/DDR3 controller supports DDR-1066 on DDR2, and DDR-1333 on DDR3, respectively. Going over these speeds is overclocking; which is never guaranteed.
Can you see how the memory is interconnected with the CPU, and not the NB as in previous generations? This is the big change which allows those massive bandwidth figures, and ultra-low latency times.
<hr>
GETTING DECENT DDR2/DDR3 SPEEDS
On DDR2/DDR3, when you go beyond about 1000 MHz with DDR2 and 1333 MHz with DDR3, there's a special thing you need to do. Most people only set CAS, tRCD, tRP and tRAS to the specified timings. While this is necessary, it is also not enough. If you're using a chipset that supports EPP/XMP, I suggest you use these profiles because the advanced memory timings will be applied. When overclocking, the advanced timings are not changed, and usually cause unstable overclocks.
The timing you need to start working with is tRFC. tRFC can go as high as 72T when you go to 1800 MHz. Download Everest, view your SPD profile, and make note of the tRFC setting in your sticks EPP/XMP profiles if you wish to overclock manually. If no EPP/XMP profiles are present, unfortunately, you will have to guess.
<hr>
Thanks for reading.
Never thought of the simple things. :lol_anim:
:lol_anim:
Instead of being stuck with 2 sticks all the time. 