MSI C236A WORKSTATION Hyper Threading Issue With Intel Skylake CPU

sunmoon2017

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Under complex micro-architectural conditions, short loops of less than 64 instructions that use AH, BH, CH or DH registers as well as their corresponding wider register (e.g. RAX, EAX or AX for AH) may cause unpredictable system behavior. This can only happen when both logical processors on the same physical processor are active
https://lists.debian.org/debian-devel/2017/06/msg00308.html
MSI C236A WORKSTATION  BIOS need microcode updates . 7998v28 BIOS was not fixed.
 

Nichrome

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Cool. MSI is aware of this, they got the microcode and will release fix whenever it's done.
 

whitakersm84

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If your system isn't blue screening and/or you aren't using your system as a research computer then don't worry about it. Otherwise disable hyperthreading. Done.
 

sunmoon2017

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I am running  Debian 9.0.0 Stretch / Linux kernel 4.13 /BIOS Version 7998v28 ,some errors in dmesg.
Code:
[    0.000000] [Firmware Bug]: TSC_DEADLINE disabled due to Errata; please update microcode to version: 0xb2 (or later)
microcode in BIOS Version 7998v28 is 0xa6.
Code:
cat /proc/cpuinfo |grep microcode |sort -u
microcode    : 0xa6

Intel CPU microcode in BIOS needs to be updated as soon as possible.
kernel source:
https://github.com/torvalds/linux/blob/master/arch/x86/kernel/apic/apic.c
 

sunmoon2017

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kernel source:
https://github.com/torvalds/linux/blob/master/arch/x86/kernel/apic/apic.c

kernel will check microcode version.
Code:
static const struct x86_cpu_id deadline_match[] = {
	DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X,	hsx_deadline_rev),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X,	0x0b000020),
	DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D,	bdx_deadline_rev),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X,	0x02000014),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE,	0x22),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT,	0x20),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E,	0x17),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE,	0x25),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E,	0x17),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE,	0xb2),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP,	0xb2),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE,	0x52),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP,	0x52),

	{},
};

static void apic_check_deadline_errata(void)
{
	const struct x86_cpu_id *m;
	u32 rev;

	if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		return;

	m = x86_match_cpu(deadline_match);
	if (!m)
		return;

	/*
	 * Function pointers will have the MSB set due to address layout,
	 * immediate revisions will not.
	 */
	if ((long)m->driver_data < 0)
		rev = ((u32 (*)(void))(m->driver_data))();
	else
		rev = (u32)m->driver_data;

	if (boot_cpu_data.microcode >= rev)
		return;

	setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
	pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
	       "please update microcode to version: 0x%x (or later)\n", rev);
}
 
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