When is it safe to reduce VCC Core Voltage for Arrow Lake?

[arnal160002e8]

VCC Core Voltage a.k.a Vcore. If my understanding is correct, for Arrow Lake this is the voltage fed from the motherboard VRM to the DLVR, which in turn feeds some of it to the CPU cores in accordance with their individual VIDs. The rest is used up by the DLVR itself.

So if P-/E-core voltages are reduced, the VCC Core Voltage should be safe to reduce too - or should it?

I have undervolted only the top points of my Core Ultra 265K's cores' V/F curve, as that's where the CPU runs hottest, is least voltage-efficient, and is most power-hungry. It's also where any long-term degradation happens fastest. My rationale for not simply applying a flat offset is explained in this post, but briefly, it would be too laborious to stability-test the whole frequency range up to 5,200MHz and the 265K already runs quite efficiently at lower frequencies out of the box.

Suppose I want to apply a flat -50mV offset to VCC Core Voltage. Since VCC Core Voltage is not static, but rather varies with the load placed on the CPU, wouldn't I also have to apply (at least) a flat -50mV offset to both the P-cores and E-cores in order for that same flat offset to VCC Core Voltage to be guaranteed safe? In other words, am I correct to assume that:

1. It is not safe to offset VCC Core Voltage by -50mV if only the P-cores or E-cores are offset by -50mV. Instead, both sets of cores have to be offset because otherwise one set of cores might be starved of the voltage they need from the DLVR?
2. It is not safe to offset VCC Core Voltage by -50mV unless a flat offset is also applied to the cores, because the Vcore varies with load, and thus even if (only) the top V/F curve points are undervolted (as in my case), and hence VCC Core Voltage could be reduced at high loads, there is no guarantee that reducing it via a flat offset wouldn't starve the CPU cores at low loads?
3. It is not safe to offset VCC Core Voltage by -50mV unless both P-cores and E-cores are both offset by at least -50mV.
4. What about the ring/cache? Is VCC Core Voltage involved with that at all? SkatterBencher explains the voltage regulation topology of Arrow Lake, but I don't know which of the concepts he mentions (VccIA, VccCOREn, VccR, VccATOMn) map to VCC Core Voltage - if any.

 

[patsc158102e1]

@arnal160002e8
Unfortunately, I can't answer your questions because, without a missing scenario, it could go one way or the other. It could be safe, or it could be unsafe.

So I'll briefly share a few insights. Always referring to MSI, so in my case, the Z890 MSI Tomahawk Wifi and my 265k CPU. I know you like skatterbencher.com, but never forget that he primarily does overclocking and UV is only a secondary aspect of his work. Second, he mostly uses Asus, which allows much more differentiated values ?? in some areas of the BIOS and isn't necessarily transferable to all settings on MSI motherboards or their BIOS.

1. The E-Core Vcore doesn't affect the VCC Core at all!

2. A negative offset to the PCore voltage alone doesn't affect the VCC Core!

3. A negative offset to the Ring voltage affects the VCC Vcore!

4. A negative offset to the ring voltage combined with a negative offset to the P-core voltage has a greater impact on the VCC Vcore!

5. A VCC Vcore offset also affects the VCC Vcore in addition to, or in addition to, the negative ring voltage and P-core voltage offset.

6. There is a minimum limit for the VCC Vcore, which is approximately 1.22 to 1.23 V. If the VCC Vcore is at 1.22 V and you set an even higher negative offset, the VCC Vcore increases again! A bug or a security feature of the platform?! I have no idea.

PCore and Ecore offset alone do not change the VCC core!

By the way, thanks for your guide on adjusting Intel Turbo Boost behavior. Very interesting. But I confess, I'm a man of pictures. The effects on performance, whether positive or negative, and the respective power consumption in the corresponding scenario would have been very interesting to see in pictures.

Greetings

 

[arnal160002e8]

@patsc158102e1 Thanks to you, I now realize I should focus on undervolting the ring next, letting VCC Core Voltage be automatically reduced by that. Two birds with one stone - what's not to like? Hopefully tuning the top end of the ring's V/F curve has a similar effect on the maximum VCC Core Voltage as a flat offset. (I don't see why it wouldn't.)

Cheers, your post was a big help!

 

[persiz154202d8]

I'm using my 265K like this almost from the beginning:
VCC Core voltage - Offset -0.150v
P Cores voltage - Offset -0.100v
E Cores voltage - Offset -0.050v
Ring voltage - Offset -0.150v

There are no problems at all. Moreover I'm using it with Disabled IA CEP and and CPU Lite Load to Mode 13

 

[arnal160002e8]

@persiz154202d8 Thanks for posting your undervolts - seeing what others have achieved is helpful for setting expectations.

I'll admit my jaw hit the floor when I saw you are using a -150mV flat offset on the ring voltage; that seems extremely high. But then I tried offsetting my ring V/F curve ratio 37x and 38x points by that amount (not immediately - I worked my way up to it) and it passed a superficial 15 runs of Cinebench R15.0.37 Extreme and 10 iterations of Linpack Xtreme. So I guess that level of undervolt might not be totally unrealistic for my sample. I still need to test way more thoroughly using something like several hours of Prime95 Small FFTs with AVX/2, though.

What did you use to stability-test your ring undervolt?

So far, undervolting just the high end of my ring's V/F curve by -150mV during Cinebench R23 has dropped my maximum CPU package temperature by ~7C and reduced my maximum Vcore by about 150mV from ~1.466V. Here is HWInfo64 after the aforementioned 10 cycles of Linpack Xtreme (my P- and E-cores are also undervolted in the screenshot):



I'm also quite taken aback that, beyond what I presume will be an indirect reduction in VCC Core Voltage from your -150mV ring undervolt, you are using an additional direct -150mV offset to VCC Core Voltage. What does your BIOS report as your VCC Core Voltage value? I'm curious whether your effective undervolt is being constrained by the ~1.22V lower limit that @patsc158102e1 mentioned.

---

And while we're sharing more broadly, I found the following maximum stable V/F curve point undervolts for my 265K's cores:

P-Cores:
- VF5 (52x): -110mV
- VF6 (54x): -115mV
- VF7 (55x): -60mV

E-Cores:
- VF6 (46x): -95mV

These are with Intel default power limits and CPU Lite Load 13. I methodically identified these by working my way to them in 5mV increments. It took a few weeks...

 

[persiz154202d8]

What did you use to stability-test your ring undervolt?

I use everything but Prime95 on Small FFTs and Blend for at least an hour on both seems to work the best.

 

[arnal160002e8]

Looks like the 265K's ring has enormous undervolt potential. I've now undervolted mine by -300mV at 37x and 38x, which is the maximum that my motherboard allows, and I still haven't encountered any instability during stress testing. At -300mV, my CPU Ring Voltage readout in BIOS is 0.948V.

For VCC Core Voltage, a -300mV ring undervolt is well past the point of diminishing returns; I haven't seen any reduction to VCore in HWInfo64 past roughly -190mV on the ring voltage. My CPU package temperature hasn't decreased by a statistically significant margin past that point either.

As outlandish as -300mV might seem, SkatterBencher reportedly reached a ring clock of 3,900Mhz at 950mV on his 285K, which is 298mV below my 265K's stock 1.248V ring voltage at 38x. Makes me wonder why the ring voltage is set so high by default...

 

[persiz154202d8]

It matters how it is set, fixed or by offset.
For instance my Ring on 3900 can do 1.000v fixed voltage but can't go offset over -0.150v which is about 1.100v at 3900.
Sometimes IMLCGui can give a good indication if the offset is too much.